The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a plurality of banks whereof I/O (Input/Output) lines consist of global and local I/O lines.
In a semiconductor memory device having a plurality of banks, there are provided global and local I/O lines. The global I/O lines are commonly provided for the plurality of banks, and local I/O lines in a bank are connected to the global I/O lines when information reading/writing of sub-arrays in the bank is performed.
FIG. 4A is a schematic diagram illustrating a configuration example of a conventional semiconductor memory device consisting of a plurality of banks.
In the example of FIG. 4A, there are illustrated two banks 110a and 110b, each comprising sub-arrays 120 arranged in matrix of rows (i=1 to 4).times.columns (j=11, 12, 21, 22).
A main word-decoder (XDEC) is provided for each row of the sub-arrays 120 and main word-lines (MWL) 131 are extending from each main word-decoder (XDEC) in an x-direction traversing the sub-arrays 120. A column-decoder (YDEC) is provided for each column of the sub-arrays 120 of each bank and column-selection lines (YSW) 133 are extending from each column-decoder (YDEC) in a y-direction traversing the sub-arrays 120.
In each of the sub-arrays 120, bit-line pairs (BL) 134 are extending from a sense-amplifier unit (SA) 121 in the y-direction, and sub-word-lines (SWL) 132 are extending in the x-direction from a right-side and a left-side sub-word driver unit (SWD), alternately, for example.
For each two columns (j=11 and 12, or 21 and 22), in the example, of the sub-arrays 120 of the two banks 110a and 110b, a read/write amplifier (R/W AMP) 150 is provided. From each read/write amplifier (R/W AMP) 150, a global I/O-line pair (GIO) 140 is extending in the y-direction traversing the two banks 110a and 110b, and a local I/O-line pair (LIO) 130 is extending in the x-direction traversing each two sub-arrays 120 arranged in a row of the two columns sharing the global I/O-line pair (GIO) 140.
For each row (i=1 to 4) of each bank, a row-activating line RACT.sub.i (i=1a to 4a in the bank 110a and 1b to 4b in the bank 110b) is provided extending in the x-direction traversing the sub-arrays 120 of the row.
Further, a column-activating-signal line (RWS.sub.i : i=1a to 4a in the bank 110a and 1b to 4b in the bank 110b) 160, which controls connection of the local I/O-line pairs (LIO) 130 to the global I/O-line pairs (GIO) 140, is extending in the x-direction traversing the sub-arrays 120 of each row of the two banks 110a and 110b. The column-activating-signal line (RWS.sub.i) 160 is enabled according to AND logic of the row-activating line RACT.sub.i and bank-selection signal RWSa or RWSb for designating a bank (110a or 110b) to be accessed, respectively.
Now, operation of the semiconductor memory device of FIG. 4A is described also referring to a circuit diagram of FIG. 4B which illustrates a circuit configuration of a part B of FIG. 4A.
When information is written into a specific sub-array 120, a row-activating line RACT.sub.i (RACT.sub.1b, for example) of a row of the sub-array 120 is raised up, and one of the main word-lines (MWL) 131 shared by the sub-array 120 is enabled by a main word-decoder XDEC, which enable one of the sub-word-lines (SWL) 132 of the sub-array 120 selected by a sub-word-driver SWD of either side of the sub-array 120,
Data to be written in the sub-array 120 is transmitted to the two banks 110a and 110b by way of a global I/O-line pair (GIO) 140 from a read/write amplifier (R/W AMP) 150 which are shared by the sub-array 120. In synchronization with data transmission, a bank-selection signal (RWSb, for example), and consequently, a column-activating-signal line (RWS.sub.1b, in the example) is enable, whereby a local I/O-line pair (LIO) 130 shared by the sub-array 120 is connected to the global I/O-line pair (GIO) 140 by a transfer gate TRG1 which becomes ON according logic of a corresponding column-activating-signal line (RWS.sub.i) 160.
At the same time, one of the bit-line pairs (BL) 134 of the sub-array 120 is connected to the local I/O-line pair (LIO) 130 by a transfer gate TRG2 which becomes ON according to logic of corresponding one of the column-selection lines (YSW) 133 selected by the column-decoder YDEC shared the sub-array 120.
Thus, the information transmitted through the global I/O-line pair (GIO) 140 is written into a memory cell MC on the bit-line pair (BL) 134 enabled by the sub-word-line (SWL) 132, of the sub-array 120.
When the information written in the sub-array 120 is to be read out, a main word-line MWL 131 and a sub-word-line SWL 132 is enabled according to rise-up of a corresponding row-activating line RACT.sub.i in the same way with information writing. Then, the local I/O-line pair (LIO) 130 shared by the sub-array 120 is connected to the global I/O-line pair (GIO) 140 according to logic of the corresponding column-activating-signal line (RWS.sub.i) 160, and, at the same time, one of the bit-line pairs (BL) 134 of the sub-array 120 is connected to the local I/O-line pair (LIO) 130 selected by logic of the column-selection lines (YSW) 133.
Thus, information stored in a memory cell MC of the bit-line pair (BL) 134 enabled by the sub-word-line (SWL) 132 is sensed and amplified by a sense-amplifier element SAE of the sense-amplifier unit (SA) 121, and transmitted through the local I/O-line pair (LIO) 130 to the global I/O-line pair (GIO) 140 to be read out and amplified by the read/write amplifier (R/W AMP) 150.
However, in conventional semiconductor memory devices such as illustrated in FIG. 4A, the column-activating-signal line (RWS.sub.i) 160 should be provided for every row of the sub-arrays 120 for controlling connection of the local I/O-line pair (LIO) 130 to the global I/O-line pair (GIO) 140, which needs number of wirings, resulting in increase of memory chip size.
Further, the column-activating-signal line (RWS.sub.i) 160 are extending in the x-direction traversing the sub-arrays 120 arranged in rows, while the column-selection lines (YSW) 133 are extending in the y-direction traversing the sub-arrays arranged in columns. In many cases, length of rows of the sub-arrays is longer than length of columns of the sub-arrays in a bank. Therefore, there may be derived skew between connecting timing of the local I/O-line pair (LIO) 130 to the global I/O-line pair (GIO) 140 and that to the bit-line pair (BL) 134, because of difference of parasitic capacitance or wiring impedance between the column-activating-signal line (RWS.sub.i) 160 and the column-selection lines (YSW) 133, resulting in access delay.